| 摘要 |
PURPOSE:To form FET pair having good matching capability in m-row and n- column array by forming a gate layer on a substrate across the drains of first row and the sources of next row, biasing them to induce charge of the type for enhancing the conductivity of the substrate. CONSTITUTION:The sources 2 and the drains 3 of FETs Q1-Q4 having equal size, and are aligned in 2-row and 2-column at equal interval at both sides of a gate insulating layer 4 at equal lateral and longitudinal distances. They are arranged at equal interval at both sides of an isolation gate insulating layer 12. Since the size and the mutual position of the respective FETs can be simply specified, the irregularity in the characteristics of the FETs due to the irregularity of the size can be reduced to obtain FET pair having good matching capability, and when a bias voltage 14 is applied to an isolating gate insulating layer 12, thereby inducing positive charge in a P type substrate 1, and weakening the electric field at the part to prevent the elongation of the depletion layer 11. Thus, the respective FETs can be further approached to each other, and the FET pair having good matching capability can be obtained. |
