| 摘要 |
A signal processor has a single random access memory having a capacity equal to or greater than the total number of words in a processing interval. An address sequence mechanism is operatively connected to the memory for addressing the memory in a sequence for, after the first processing interval, reading out data for the first processing interval continuously in a preselected output order and overwriting data for the next processing interval continuously in a preselected input order in the locations of the data being read out. An address checker is connected to the address sequence mechanism for checking the addresses thereof for error and a controller is operatively connected to the address sequence mechanism, address checker, and memory for controlling their operation.
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