发明名称 MULTIPLEX OUTPUT COLLATION SYSTEM
摘要 PURPOSE:To process the collation of multipoint data with one data collation set, by making collation through the readout of the content of registers which are accessible, and transmitting the coincidence data as the address for the counter value to the output device. CONSTITUTION:Data outputted from each duplex CPU(not shown) via buses 101, 102 are inputted to registers 51, 52. The write-in address of the data section is designated with the address of the buses 101, 102 and the readout address of data is designated with the value of a counter 53. The data of the registers 51, 52 designated with the counter 53 is collated 54, and only when they coincide, the data is outputted to a bus 103 by taking the value of the counter 53 as the address section. If uncoincidence of data has been observed for longer than a prescribed time, an error signal is transmitted.
申请公布号 JPS5745653(A) 申请公布日期 1982.03.15
申请号 JP19800121082 申请日期 1980.09.03
申请人 HITACHI SEISAKUSHO KK 发明人 YAMAOKA HIROMASA;IWASA YUUZABUROU
分类号 G06F11/18;G06F11/16;G06F13/00;G06F15/16;G06F15/177 主分类号 G06F11/18
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