| 摘要 |
<p>PURPOSE:To directly pick up a clock signal of a differentiation mark transposition code train with a simple constitution, by adding the differentiation mark transposition code train to a delay circuit, AND circuit and NOR circuit and outputting the sum via an FF, and logical circuit of exclusive logical NOR circuit. CONSTITUTION:A delay circuit DLY delays a differentiation mark transposition DMI code train (a) by T/2 (where: T=1/f0, and f0 is a clock frequency) to output a code train (b). The output (c) of an AND circuit for input code trains (a) and (b) corresponds to a binary non-zero return NRZ data 1 coded at 11, and the output (d) of an NOR circuit NOR in which the logic is at inversion (a+b) corresponds to 1 of the NRZ data coded to 00. The FF is set to leading of the signals (c), (d) and a signal (e) is applied to one terminal of an exclusive logical sum NOT circuit ENOR. A code train (b) is applied to another input terminal of the circuit ENOR and the signal (c) is applied to other input terminal, and an output (f) of the circuit ENOR is applied to an OR circuit OR with the signal (d) and a clock signal (g) in frequency f0 is outputted from the circuit OR.</p> |
