| 摘要 |
PURPOSE:To increase high-speed clock pulses with a pulse increase signal outputted from an equipment whose operation speed is low by synchronously shaping the pulse increase signal to one period width of the clock pulses and by exclusively ORing the shaped signal with the clock pulses. CONSTITUTION:At the rise of a pulse increase signal, a D type flip-flop (D-FF)111 is set and at the following fall of the clock pulse, a JK type flip-flop (JK-FF)12 reads the output of the D-FF111. At the rise of the next clock pulse, D-FF112 is set, so the output Q' goes to a level L, resetting the D-FF111. Then, the output of the JK-FF12 is inverted at the fall of the clock pulse and the D-FF112 is reset at the rise of the next clock pulse. The output Q' is applied to an exclusive OR circuit 17 through a delay circuit 16 to be exclusively ORed with the clock pulse thereby increasing one clock pulse. |
