| 摘要 |
PURPOSE:To increase the transfer efficiency of memory, by providing registers provided with individual address lines and data lines for readout and write-in. CONSTITUTION:At write-in, a central processor initially sets the control information to an address of a register file 203. When a request signal to a channel is taken place, a channel request reception circuit 301 makes reception at the 1st timing T0. When the control information of the register file 203 is read out at the next T0 signal, the content of the register file is renewed and data is written in a data buffer 202. At readout, the central processor initially sets the control information to the address in the register file 203. At the 2nd timing T2, the readout address of a memory request address buffer 322 is indicated and data is written in the data buffer at the next T2 signal. The T0 and T1 signals control the register file alternately to execute the readout/write-in at the same time. |
