发明名称 INPUT AND OUTPUT PROCESSING SYSTEM
摘要 <p>PURPOSE:To increase the input and output speed and to improve the system efficiency, by increasing the capacity of input and output registers and providing plural registers. CONSTITUTION:An input and output instruction information produced from a CPU is written in the memory address designated with an address line. For example, addresses 0-7 are assigned to the input and output instruction information, then a flag 1 is set to 1 at the address 7. The input and output processor detects it and advances a counter 12. When the CPU desires to write in data, it is started from the next area, i.e., address 8. Thus, the data is written in sequentially to the succeeding areas. The input and output processor reads in the memory via the address line, and after read-in, the flag 1 is set to 0. Thus, the data are read in one after another.</p>
申请公布号 JPS5743222(A) 申请公布日期 1982.03.11
申请号 JP19800118733 申请日期 1980.08.28
申请人 TOKYO SHIBAURA DENKI KK 发明人 KIMURO SHIGEO
分类号 G06F13/14;G06F13/12;G06F15/78 主分类号 G06F13/14
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