发明名称 TIMING CIRCUIT
摘要 <p>A phase locked loop (PLL) tuning system for generating a local oscillator signal includes a programmable divider having a programmable division factor related to the frequency of the local oscillator signal. The programmable factor is determined by the duration of output pulses generated by a triggerable circuit in response to input trigger pulses generated by the PLL. The duration of the output pulses is adjustable by means of a potentiometer included in an R-C time constant network associated with the triggerable circuit. A reference divider associated with the PLL generates reference trigger pulses and reference time pulses in a substantially fixed time relationship during time intervals between output pulses generated in response to the input trigger pulses. The triggerable circuit generates comparison output pulses in response to the reference trigger pulses. The fixed time interval is related to the nominal values of the durations of the comparison output pulses. A comparison circuit generates a control signal in accordance with the time relationship between the termination of the comparison output pulses and the reference time pulses. The control signal is coupled to the time constant network to reduce deviations between the duration of the comparison output pulses and the fixed time relationship.</p>
申请公布号 GB2003351(B) 申请公布日期 1982.03.03
申请号 GB19780034116 申请日期 1978.08.22
申请人 RCA CORP 发明人
分类号 H03L7/18;H03J5/02;H03K9/08;H03L7/199;H03M1/00;H03M1/56;H04B1/26;(IPC1-7):03K3/00;03K13/20;03B3/08 主分类号 H03L7/18
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