| 摘要 |
<p>PURPOSE:To shorten output response time in a microcomputer and to realize synchronous property in an output signal by accessing a table area with an address changeover circuit by address information from an output port of a CPU and by latching information of a data bus. CONSTITUTION:In a case where a necessity occurs that states of controlling outputs OUT0-7 are changed simultaneously and immediately in response to occurrence of an external interruption, table area address signals comprising E0-E3=''1111'' are outputted from a certain output port E of a microprocessor CPU1. Then, by the fact that a signal becomes high potential, an output (f) of an FF in a clock signal generating circuit 2 becomes high potential, E0-E2 are substituted to the lower 3 bits of an address bus (a) by an address changeover circuit, and ''1'' is obtained at >=4 bits, thus allowing ''100011101'' to be outputted. At that time, a clock signal (t) becomes high potential, contents of a data bus (g) are latched, and outputted as OUTs 0-7.</p> |
