| 摘要 |
<p>PURPOSE:To realize a high-speed memory operation, by adding a variable resistance means whose resistance value becomes smaller in the reading preparatory period than the reading period of a memory cell between a power source and the memory cell. CONSTITUTION:A control circuit CTN of a gate transistor TRQG is formed, and a signal P which is set at ''H'' and ''L'' in the reading period and the reading preparatory period respectively is applied to the gate of a TRQ34. While a signal P' is applied to a TRQ35. In such circuit, the signals P and P' are set at ''L'' and ''H'' respectively in the reading preparatory period with TRQ33 and TRQ34 turned off, and the potential of a node N2 is set at ''H'' by the VCC. Accordingly the TRQG is turned on with the reduced resistance value, and thus a node NO can be set at ''L'' in a short time. On the other hand, the signals P and P' are set at ''H'' and ''L'' respectively in the reading period with the TRQ33 and TRQ34 turned on. At the same time, the potential of the node N2 is set between the VCC and the earth potential, and the TRQG is turned off at the time point when a node N1 slightly rises up. Thus the node NO can be quickly set at ''H''.</p> |
