| 摘要 |
PURPOSE:To improve the reliability of instruction buffers and to achieve continuous processing by providing two instruction buffers to an electronic computer wherein two instruction units are capable of operation, and by changing in-use modes at an adequate point in time. CONSTITUTION:Two instruction buffers 3-A and 3-B in which a fill bit is entered and which have plural entries are provided; when a BRANCH or EXECUTE instruction is detected as an instruction read out of a prescribed main instruction buffer 3-A, an instruction at a BRANCH destination or a SUBJECT instruction is stored previously in the subordinate instruction buffer 3-B and required operand address calculation is finished, so that continuous processing is achieved. Normally, coincidence between instructions read out of the main instruction buffer 3-A and subordinate instruction buffer 3-B is detected, so invariably correct instructions are supplied to instruction execution units. |
