| 摘要 |
Each bistable cell of a memory matrix is uniquely accessed through a row transistor and a column transistor connected in series between one node of the bistable cell and the data-in. During WRITE, a single row is accessed activating all of the gates on the row transistors of that row, and a single column is accessed activating all of the gates on the column transistors of that column. Only the addressed cell at the intersection of the accessed row and column has both the row and column transistors turned on establishing a conductive path to the data line. All of the remaining cells on the accessed row and column have only one of their access transistors turned on. The other access transistor of these partially accessed cells remains non-conductive. The data-in on the data line is either high ("1") or low ("0") driving the addressed cell into one of two storage states. During READ only the addressed cell at the intersection of the accessed row and column has a conductive path to the high read voltage on the data line. The storage state of the addressed cell causes the data line voltage to either load down or to remain high. Write and read disturb are prevented because all of the remaining cells have at least one of their two access transistors turned off. The write and read isolation reduces the cell stability requirement to a very small trickle current necessary to maintain the node capacitance in the cell. The charge on these capacitances may be replenished periodically by charge pumping the load device. Read disturb of the accessed cell is avoided by employing a regenerative sense amplifier which restores the accessed data after each read cycle.
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