发明名称 PLL FREQUENCY SYNTHESIZER TUNER
摘要 PURPOSE:To prevent the production of tracking error, by using separate PLL circuits for local signal frequency and tuning voltage for RF amplifier. CONSTITUTION:PLL circuits 6, 8 are provided and a controller 7 and a reference oscillator 61 are used in common. The output of the PLL circuit 8 is applied to an RF amplifier, and the output of the PLL circuit 6 is applied to a mixer MIX3. The frequency dividing ratio of frequency dividers 82, 62 is changed. For example, taking the RF reception frequncy fr as 531-1602kHz, frequency between stations as 9kHz(=fs), RF signal frequency as 468kHz, local signal frequency f as 999(531+468)-2070(1602+468)kHz and frequency fs of a reference oscillator 61 as 9kHz, respectively, the relation among the frequency dividing ratio N of the frequency divider 62 and the frequency dividing ratio N' of the frequency divider 82 is N'=N-52.
申请公布号 JPS5721132(A) 申请公布日期 1982.02.03
申请号 JP19800096391 申请日期 1980.07.15
申请人 PIONEER ELECTRONIC CORP 发明人 ADACHI HIROO
分类号 H03L7/18;H03J5/02;H03J7/28;H03L7/22;H04B1/26 主分类号 H03L7/18
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