| 摘要 |
PURPOSE:To increase the amount of storage charge, by applying a storage line signal in which it becomes low level after the word line signal is at high level and it becomes high level before it is at low level, to the gate of an MOS capacitor. CONSTITUTION:A bit line receives a signal charge at time t1 and it is set to an equal voltage at both sides of a sense circuit. At time t2, the word line signal is set at high level and a storage line signal S is set at low level, a singl charge 10 is transmitted to the bit line and a change on the bit line signal BL is caused through the presence or absense of the signal charge. The sensing by the sense circuit is made at time t2 and time t3, ant the bit line potential is set at high or low level according to the information. At time t4, the word line signal T remains at high level and the storage line signal S is brought to a high level. At time t5, since the word line signal T is brought to a low level, the information is fetched to the memory cell. |
