发明名称 CLOCK SWITCHING CONTROL SYSTEM
摘要 PURPOSE:To increase the reliability of a duplex data processor of master-slave system, by using a normal clock generator of one of the data processor in common for both data processors. CONSTITUTION:In case systems A and B work as a master and a slave processor, respectively, master-slave deciding circuits 13 and 14 deliver 0 and 1 output lines 25 and 26, respectively. Accordingly, a clock switching circuit 5 supplies the clock of a clock generating circuit 15 of its own system to a logical circuit 11; and a clock switching circuit 6 supplies the clock of the circuit 15 of the other system to a logical circuit 12. Under such condtitions, if a trouble of function arises in the system A to cause the necessity of switching between the master and slave processors, the clocks are supplied to the circuits 11 and 12 of both systems from a clock generating circuit 16 of system B. In such way, the maintenance can be facilitated for the data processor since the clock generating circuit of a duplex data processor is not used in common. Thus the reliability can be enhanced.
申请公布号 JPS5714923(A) 申请公布日期 1982.01.26
申请号 JP19800090374 申请日期 1980.07.02
申请人 PANA FACOM KK 发明人 TAKEGAWA TERUAKI;SUZUKI AKIHIKO;NAKA KENICHI;FUTAKI JIYOUICHI
分类号 G06F15/16;G06F1/04;G06F15/177 主分类号 G06F15/16
代理机构 代理人
主权项
地址