发明名称 INPUT/OUTPUT SYSYTEM
摘要 PURPOSE:To enable a central processor to process an input/output data in the form of a fixed length data in a system using a variable length code, by putting an invalid code into an idle region. CONSTITUTION:A data process system comprises with a mutual connection among an input device 1, a central processor 2 and an output device 3 via data buses 4 and 5. The variable length character code is transferred by a byte in the device 1 to a buffer register 7 from a data buffer 6 via a counter circuit 9. In this case, the circuit 9 counts the number of bytes of the character code to be transferred to the register 7 and then report the end of transfer to a data control circuit 10. Receiving this report, the circuit 10 puts an invalid code into the rest part of the register 7 and then transmits it to the processor 2 in the form of a fixed length daga. The device 2 eliminates the invalid code for delivery of an output through an output deciding circuit 12.
申请公布号 JPS5714944(A) 申请公布日期 1982.01.26
申请号 JP19800090136 申请日期 1980.07.02
申请人 HITACHI LTD 发明人 TSUYUKI YOUSUKE;YAMAZAKI AKIRA
分类号 G06F5/00;G06F13/00;H03M7/40 主分类号 G06F5/00
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