| 摘要 |
<p>PURPOSE:To correct the timing of data read-in automatically, by counting the basic clock through the detection of the l-th bit of a start signal and controlling the number of stages of a number of stage variable ring counter with this output. CONSTITUTION:When the l-th bit of a start signal of a serial binary code consisting of the start signal and a data signal for one frame is detected at an l-th bit detecting circuit 22, the output is at 1 and the output of a basic clock oscillator 21 is introduced to a counter 24 via an AND circuit 23. The content of the counter 24 is inputted to a decoder 25 and the number of stage of a number of stage variable ring counter 26 is controlled according to one bit period of the l-th bit of the input serial binary code. Thus, the timing clock being the output of the counter 26 changes the phase of production in response to the length of the one bit period and the data read-in timing pulse can be obtained at the center of each bit of the data signal from a timing pulse generating circuit 27.</p> |
