| 摘要 |
PURPOSE:To read out at the same time contents of an optional address of a memory which stores a digital data, in a logic analyzer for displaying an hourly variation of a digital signal of plural channels. CONSTITUTION:A controlling circuit 16 writes a data being equal to a delay count value of a delay counter in a memory 15, and thereafter, stops updating an address counter 17 by outputting a write end signal, latches contents of that time point to a latching circuit 19, selects an output of an address operating circuit 21 by switching an address switching circuit 18, and also sets the memory 15 to a read-out mode. Accordingly, when a suitable address data is set to the address operating circuit 21 from a central operation proceesor 22, an optional address data can be obtained by adding or subtracting it to or from the latch contents. Subsequently, by this data, an address of the memory 15 is selected through the address switching circuit 18, and a data stored in the address concerned can be read out to a data bus of a bus 27. |
