发明名称 PARALLEL PROCESSING SYSTEM
摘要 PURPOSE:To shorten the entire processing time, by performing data access and arithmetic simultaneously in parallel after fetching instructions. CONSTITUTION:In the address of the step (n) of a program memory 12, its arithmetic instruction 1 and operand information 2 of the next step are stored. When the instruction 1 is read out of the memory 12 and then decoded by an instruction decoder 13, the instruction 1 is executed immediately because data of the instruction 1 are supplied from a data bus 10 and an arithmetic register 15. Simultaneously with the execution of the instruction 1, the operand information of the next arithmetic instruction 2 is supplied from the decoder 13 to an address register 16, so the arithmetic and access to a data memory 18 for data required for the next arithmetic instruction are performed. Address data inputted to the registe 16 is shifted to an address register 17 before being rewritten in address data of the information 2.
申请公布号 JPS578851(A) 申请公布日期 1982.01.18
申请号 JP19800081359 申请日期 1980.06.18
申请人 FUJI ELECTRIC CO LTD 发明人 EBIHARA MASAYUKI
分类号 G05B19/05;G06F9/38 主分类号 G05B19/05
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