| 摘要 |
PURPOSE:To receive a variable-length data statement efficiently by permitting a control circuit to eliminate the need to monitor a received signal while receiving data, by providing a calculating circuit for the number of words and a delay circuit. CONSTITUTION:A received bis-serial signal (a) is converted by series-parallel converting circuit 10 into byte-serial data, which is stored in a buffer memory BM11. A control circuit 12, two bytes, for example, after a store signal (b) goes to an ''H'', opens receiving gates 13 and 14, and the data in the BM11 are inputted to a control circuit 12 and a calculating circuit 15 for the number of words. The calculating circuit 15 calculates the number of words of the remaining data and then sends a calculated value to the control circuit 12. On the basis of the value, the control circuit 12 starts a delay circuit 16 and carriers out its original operation during the period. The control circuit 12 opens receiving signal 13 and 14 again with a timer end signal (f) from the delay circuit 16, and fetches and processes data as many as the number of words calculated by the calculating circuit 15. |
