| 摘要 |
PURPOSE:To accomplish an arbitrary amount of phase shift in an arbitrary step by digital control, by using a phase locked loop (PLL) and a counter. CONSTITUTION:A signal applied to an input terminal 1 is respectively given to a PLL circuit 2, phase comparator 3, set terminal S of an FF7 and load terminal L of a programmable counter 8, and a signal multiplying the input signal by N, where the frequency dividing ratio of a frequency divider 6 is N, is applied as a clock to a clock terminal CLK of the programmable counter 8 from a VCO 5. Further, an output at a termnal Q of the FF7 is applied to an enable terminal E of the programmable counter 8 and the output signal is applied to a reset terminal R of the FF7. When a control signal S1 sets the frequency dividing ratio of the frequency divider 6 as N and a control signal S2 sets the number of counts of te counter 8 as M, the signal phase is (360XM/N). |
