| 摘要 |
PURPOSE:To secure the same constitution for the receiving part regardless of the style of the received data to realize a simplification, by carrying out a series-parallel conversion not at the receiving part but at the side of the data processing part. CONSTITUTION:The rise and fall of the received data D are detected at detecting circuits 11 and 12, and a signal generating circuit 13 is started. The circuit 13 produces both a sampling pulse C and an interruption signal E at a time with every 1/2 bit length. Thereafter, the pulse C and signal E are produced with every bit length. The data D is set to a data receiving circuit 14 consisting of a flip-flop FF by the pulse C, and an interruption is then applied to a data processing part 15 with the signal E. The part 15 reads the 1-bit data F given from the circuit 14 and carries out a series-parallel conversion of data on an RAM as well as a synchronous detection. |
