| 摘要 |
PURPOSE:To attain high-speed access by using complementary FETs without increasing occupied area, by decoding an address signal through an intermediate item signal by using two couples of decoder circuits in prescribed arrays. CONSTITUTION:A two-bit address signal from an address buffer circuit 1 is decoded by the unit decoding circuit of the 1st decoder circuit 2 into an intermediate item signal of three bits, etc. This signal is further decoded by the 2nd high-speed decoder circuit 4 which uses complementary FETs between the 1st and 2nd memory arrays 7 and 8 to access rows of arrays 7 and 8 through word driving circuits 5 and 6. Therefore, switch elements of circuits 2 and 4 are decreased in number in comparison with when an address signal of six bits, etc., is decoded by a single decording circuit, and an address is decoded substantially by the circuit 5 and 6 to make the number of unit decoding circuits of the circuit less than the number of word lines of the arrays 7 and 8. Consequently, high-speed operation is performed by using the complementary FETs without increasing occupied area. |
