| 摘要 |
<p>A one word n bit data processor comprises several registers of (n+m) bits provided for the common use of the general purpose registers and address expansion registers. Effective addresses of (n+m) bits are obtained by adding the addresses of equal to or less than n-bits in the instruction and the content of (n+m) bits of one register designated by said instruction. The invention permits expansion of the address bit length and flexible addressing without requiring much hardware.</p> |
