| 摘要 |
PURPOSE:To eliminate the need for signal lines for the purpose of bus use request and simplify the interface between respective devices by using a bus time-dividedly in a data processor. CONSTITUTION:A central processor 1, a main storage device 12 as well as input/ output control units 2, 3 are connected by means of a bus 11. If the processor 1 desires to transfer data directly to the device 12 by using the bus, it sets a bus use request register 26. The bus use request enable signal from a bus controlling circuit 4 is brought to a high level in the second half of the bus cycle B, by which the output of the register 26 is applied to an address AD0, and the bus use request from the input/output devices is aplied to an address AD1. The bus use request signal is fetched into the detecting latch 20 of a control circuit 4, and the bus use permission signal is transmitted by signal lines 8-10 to the one device selected by deciding priority, whereby the main memory device 12 can be accessed while the bus use request enable signal is the low level. |
