| 摘要 |
<p>An interpolative analog-to-digital converter comprising an integrator (77) for integrating the difference between an input analog signal x(t) and a quantized signal q(t) to develop an integrated signal, a first comparator (78) for sampling the integrated signal at a first sampling frequency and for generating first signals of one data state when the integrated signal is positive and of another data state when the integrated signal is negative, a second comparator (91) for comparing the input signal x(t) to the quantized signal q(t) and for sampling the results of the comparison at the first sampling frequency to develop second signals of one data state when the input signal x(t) is greater than the quantized signal q(t) and of another data state when the input signal x(t) is less than the quantized signal q(t), logic circuitry (93) responsive to the first and second signals and operative to develop a plurality of signals including a sign bit signal, a shift left signal, a shift right signal and a no shift signal, a shift register (98) responsive to the shift left signal, the shift right and the no shift signal and operative to develop a series of multi-bit binary words each having a predetermined number of bits and a magnitude determined by the shift and no shift signals, a digital-to-analog converter (80) responsive to the binary words and the sign bit signal and operative to convert the binary words into the quantized signals q(t), the quantized signals q(t) being positive or negative dependant upon the data state of the sign bit, and a digital signal processor (101) for digitally filtering the series of binary words and for developing binary output signals at a frequency of at least twice the highest signal frequency in the input signal x(t).</p> |
