| 摘要 |
PURPOSE:To receive an information signal multiplexed in the plural horizontal periods of a vertical flyback line of a TV signal, by using a buffer memory which can record multiplexed information signals during plural horizontal periods. CONSTITUTION:The 1st address counter circuit 9 counts a clock signal outputted from a clock generating circuit 4 in synchronizing with the information signal and the output is inputted to a lower rank bit of address of a buffer memory 8 at a horizontal period in which the information signal is multiplexed at an address switching circuit 7. On the other hand, the 2nd address counter circuit 10 counts the number of horizontal periods multiplexed with the information signal and the output is inputted to an upper bit terminal of the memory 8 at the horizontal period when the information signal is multiplexed. |
