| 摘要 |
PURPOSE:To realize an enhancement-type constitution for both an MOS capacity and an MOS transistor which from a DRAM working on a single power source, by connecting a MOS capacity gate electrode to a high voltage line connected to a boosting circuit and a clamping circuit. CONSTITUTION:When a clock psi is at a low level, a terminal N2 is charged up to a potential of VDD-Vth through an MOS diode T1. The potential of N2 is increased to VDD or higher through a coupled capacity C when the clock psi is set at a high level, and further the potential of a high voltage line 7 is increased to VDD or more through an MOS diode T2. The electric charge is supplied to a line 7 from a power source through T1 and T2 with every period of the clock psi. The potential of the line 7 is clamped to VDD+Vth by a transistor T3 of a clamping circuit 9. A high- level potential of a word line is increased to VDD or higher, and thus the potential of the ''1'' information that is accumulated at a storage terminal of each memory cell can be set at VDD. |
