发明名称 PIPELINE CONTROL SYSTEM
摘要 PURPOSE:To improve the execution processing capability of instructions, by performing the pipeline processing for preparation of respective operands of instuctions besides the pipeline processing between instructions. CONSTITUTION:Instructions I1-I3 have two operands respectively. In the first cycle t1, instruction words of the instruction I are read IF<1>. In the next cycle t2, the OP code part and an addressing designation part of the first operand are decoded. In the next cycle t3, the effective address of the first operand is calculated in accordance with the decode result, and an addressing designation part of the second operand is decoded. In the next cycle t4, the first operand is ferched, and the effective address of the second operand is calculated. Thus, the pipeline processing for preparation of respective operands of instructions is performed to improve the execution processing capability of instructions.
申请公布号 JPS56162153(A) 申请公布日期 1981.12.12
申请号 JP19800065267 申请日期 1980.05.19
申请人 HITACHI LTD 发明人 MATSUMOTO HIDEKAZU;BANDOU TADAAKI;MAEJIMA HIDEO
分类号 G06F9/30;G06F9/318;G06F9/32;G06F9/38 主分类号 G06F9/30
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