| 摘要 |
PURPOSE:To reduce address transfer times and to improve the use efficiency of bus by performing the information transfer between a cash memory and a main memory by way of a common bus time-dividedly, and forming the relative addresses in blocks on both memory side. CONSTITUTION:At the cash miss, the output gate 34 of a cash memory 26 opens and an address is applied via a common bus 27 to the memory address register 36 of a main memory control part 23. Thence, the addresses excluding low-order bits are set in the register 36 via the control circuit 39 of the circuit 23, the lowest-order bit address is preset in a counter 37, and the information is read out from a main memory 22, and is written into a cash memory part 33 via a read register 38 and the bus 27. At the same time, the counter 37 is stepped by the circuit 39, and the continuous block information of the memory 22 are read out. Hence, the information transfer is processed time-dividedly by way of the common bus. |
