| 摘要 |
<p>PURPOSE:To realize high-speed parallel operation, by distributing a part of the main storage in each central processor. CONSTITUTION:Respective central processor 30-3n obtain memory address 100 by respective storage device access circuits 80-8n in execution of instructions; and if this address indicates format 100 of the address of the storage device in the processor the central processor sees central processor identification number 102 to decide whether the storage device in the central processor itself or the storage device in another unit should be accessed. When central processor identification number indicates another central processor, it is reported to another central processor through interdevice communication line 7, and the processing of this processor is interrupted, and data is obtained through the second data lines 60-6n and storage switching control device 2. If memory address 100 indicates format 200 of the address on the main storage, an instruction or data is obtained from main storage 1 through the second data lines 60-6n, storage switching control device 2, and the first data line 5.</p> |
