| 摘要 |
PURPOSE:To output two input pulses overlapping each other as two pulses which do not overlap each other, by differentiating two input pulses individually to generate two driving pulses of a prescribed width and by generating a switching pulse by overlapping of driving pulses. CONSTITUTION:Addition pulse (a) is differentiated by delay inverter IN11 and NAND gate G11 and is outputted as pulse (j) delayed in delay buffer BF by time gamma0. Subtraction pulse (b) is differentiated by IN12 and NAND gate G12 to generate pulses (g) and (h) which are delayed in delay buffers BF2 and BF3 by times shorter and longer than time gamma0, respectively, and these pulses (g) and (h) are inputted to NOR gates G17 and G18. Pulses (a) and (b) pass through delay buffers BF4 and BF5 and NAND gates G13 and G14 to generate driving pulses (c) and (d) of a prescribed width, and overlapping of these pulses (c) and (d) is extracted by NOR gate G15 and is inputted to the FF as driving pulse (e). Switching pulse (f) is generated from the FF and is inputted to gates G17 and G18, and the output is outputted through OR gate G19 to output pulse (i) separated from pulse (j). |
