| 摘要 |
PURPOSE:To realize an interface between digital devices on a less circuit scale, by preventing coincidence of timing between a read side and wire side by generating pulses, faster than the operation frequency of a digital device, by a timing generating circuit. CONSTITUTION:A data signal to be written in storage circuit 13 is applied to input terminal 12 and its write address is also applied to terminal 2 to write the data in circuit 13 with an L-level timing signal inputted to terminal 3 of timing pulse generating circuit 22. To read the data out of circuit 13, a read address is applied to terminal 4 and an L-level timing signal inputted to terminal 5 of circuit 22 is used. One of two addresses from terminals 2 and 4 is selected by selecting circuit 14 and the output of circuit 13 is held in holding circuit 15. A timing pulse from circuit 22 is applied to circuits 13-15, which are operated with pulses faster than the operation frequency between digital devices to equalize the read operation of circuit 13 to one bit width of the clock pulse. |
