| 摘要 |
PURPOSE:To eliminate the variation in a well potential due to the capacitive connection to a signal line in a semiconductor integrated circuit device by forming the same conductivity type and higher impurity density buried region as a well region and than the well region at the bottom of the well region. CONSTITUTION:A high impurity density P<+> type buried region 11 is formed in an N type Si substrate 10. A low impurity density P type well region 12 is formed on the surface of the substrate 10, and an N-channel MOSFET QN and a P-channel MOSFET QP are formed adjacent to one another. Electrodes and wires necessary to form an inverter circuit are formed in the FETs QN and QP. Since the region 11 is thus formed, the impedance of the region 12 is low, and a sufficient substrate potential is supplied from a P<+> type contact region through the region 11 to the substrate corresponding part of the FET QN. Accordingly, it can reduce the variation in the well potential due to the capacitive connection or the like to the signal line and stabilize the threshold voltage characteristics of the FET QN. |
