| 摘要 |
PURPOSE:To reduce the frequency of retrial for a transfer action of input/output data of a channel having a low priority, by delivering the highest priority storage access request in case the input/output data buffer is filled for the main memory access request of the input/output channel. CONSTITUTION:The access request to be given to the main main memory 1 from the input/output channels 3-1-3-n having the input/output data buffers is processed along with the request given from the central processor 2 with the priority decided by the priority deciding circuit 4. In this case, the highest main memory access request signal is sent to the circuit 4 via the connection lines 11-1-11-n, and the main memory access request of other input/output channels and the like is set temporarily under a queuing mode. Then a memory cycle is allotted with the highest priority to avoid an occurrence of the data erasion for the input/output device. Under such conditions, the input/output data is transferred. |
