发明名称 FLOW CONTROLLED PULSED SERIAL LINK
摘要 <p>Apparatus for transmitting a clock and data from a first module to a second module connected by a single outward line and a single return line, comprising: means for transmitting a data pulse on the single outward line comprising means for asserting a first edge on said single outward line, said first edge representing a timing edge for the clock and means for asserting a second edge on the single outward line a selectable time period after said first edge, said selectable time period representing said data; and means for receiving a return pulse on said single return path comprising means for receiving a first edge and a second edge on the single return line, the first and second edges being separated by a first time period, said first time period representing an acknowledgement.</p>
申请公布号 WO2006090109(A1) 申请公布日期 2006.08.31
申请号 WO2006GB00430 申请日期 2006.02.08
申请人 STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LTD;WARREN, ROBERT, GEOFFREY 发明人 WARREN, ROBERT, GEOFFREY
分类号 H04L1/16;H04L1/18;H04L5/14;H04L25/49 主分类号 H04L1/16
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