发明名称 |
MEMORY DEVICE WITH VERTICAL TRANSISTOR AND FABRICATION METHOD THEREOF |
摘要 |
A method for fabricating a vertical transistor. At least one deep trench is formed in a silicon substrate. A conductive structure and a trench top insulator are successively formed in the deep trench, in which the conductive structure comprises a first doping region and the trench top insulator is below the surface of the silicon substrate. An epitaxial silicon layer is formed on the surface of the silicon substrate. Ion implantation is performed in the epitaxial silicon layer to form a second doping region therein. A gate structure is formed on the trench top insulator, protruding from the surface of the epitaxial silicon layer and adjacent to the sidewalls of the epitaxial silicon layer and the deep trench. A capping layer is formed on the epitaxial silicon layer. The invention also discloses a memory device with a vertical transistor and a method for fabricating the same.
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申请公布号 |
US2008067569(A1) |
申请公布日期 |
2008.03.20 |
申请号 |
US20070751572 |
申请日期 |
2007.05.21 |
申请人 |
NANYA TECHNOLOGY CORPORATION |
发明人 |
CHEN SHENG-TSUNG;LIN SHIAH-JYH;LEE CHUNG-YUAN |
分类号 |
H01L27/108;H01L21/8242 |
主分类号 |
H01L27/108 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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