发明名称 ERROR CONTROL SYSTEM OF MEMORY DEVICE
摘要 PURPOSE:To utilize effectively a memory device having defection, by enabling an error within a permissible limit to be processed continuously by providing an error frequency counting means and comparing means. CONSTITUTION:An error signal outputted from read control circuit 3 is inputted to error control circuit 5. At time 1 in the figure, counter 30 of circuit 5 is reset. Next, as the error signal is generated once at some time 2 corresponding to the occurrence of a read error, the value of counter 30 becomes ''1''. Similarly, the error signal is outputted (n) times up to a certain time and counter 30 goes up to (n); if it is greater than error permissible frequency N held in constant holding register 31 of circuit 5, comparing circuit 32 outputs an error over signal. On the other hand, if N is greater than (n), namely, if it is within the error-occurrence permissible limit, counter 30 is reset with the output signal of timer 4 at time 3 in the figure and repeats the said operation again. In this case, no error over signal is generated, so that the data processing will be continued.
申请公布号 JPS56140598(A) 申请公布日期 1981.11.02
申请号 JP19800041721 申请日期 1980.03.31
申请人 FUJITSU LTD 发明人 USAMI RIYUUICHI
分类号 G06F12/16;G06F11/00 主分类号 G06F12/16
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