| 摘要 |
PURPOSE:To process data from a controller at a high speed by eliminating the need for software processing for data recognition, by preventing an abnormal data outputting state by providing D type edge trigger FF for priority processing control in each controller. CONSTITUTION:To central processor (CPU), controllers 1 and 2 are connected via a common bus line and in those controllers 1 and 2, D type edge trigger FFs 1g and 2g for priority processing are provided; set outputs of FFs 1d and 2d and signal IN from CPU are supplied to their data inputs and clock inputs. Further, the set outputs of FFs 1g and 2g and those of FFs 1d and 2d are ANDed by AND gates 1h and 2h, respectively. Then, FFs 1g and 2g are reset from the rise of the clock signal CLK to the fall of signal IN. While signal IN is outputted, data from devices 1 and 2 are prevented from being outputted in the same time zone and outputs of NOR gates 1e and 2e are outputted to a priority sequence controller. |
