发明名称 INTER-PROCESSOR INFORMATION TRANSFER SYSTEM
摘要 PURPOSE:To perform information transfer between processors rapidly by transferring information via a temporary memory the processors can control direct. CONSTITUTION:Processor 11 discriminates data stored in program memory 14 to send address information on temporary memory 32 onto address bus 13, and then sends information to be transferred onto data bus 12. The address information is sent to memory 32 via address discriminating circuit 17. The transfer information sent via bus 12 is also sent to memory 32. Next, processor 21 sends the address information on memory 32 onto address bus 23 and opens gate circuit 25 to sends the address information to memory 32. On the other hand, memory 32 sends information stored in the assigned address to processor 21. Thus, the inter-processor information transfer is carried out easily and rapidly.
申请公布号 JPS56135260(A) 申请公布日期 1981.10.22
申请号 JP19800037073 申请日期 1980.03.24
申请人 NIPPON ELECTRIC CO 发明人 FUJITA KAZUNORI
分类号 H04Q3/545;G06F12/00;G06F12/06;G06F13/38;G06F15/16;G06F15/167 主分类号 H04Q3/545
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