| 摘要 |
PURPOSE:To reduce alignment margin generated in a resist film forming process of MOSFET by a method wherein a poly-Si layer in a source, drain region is left when a gate structure is made and then it is removed to form contact hole. CONSTITUTION:Layer composed of a gate film 2 arranged on a base plate 1 and separated by oxidation film 7, a poly-Si 3, an oxidation film 4 and a nitride film 5 is etched to a surface of the base plate with a resist pattern 6 arranged at such positions as used in forming gates and contact holes. Reverse conductive dipersion layers 8, 9 are arranged on the base plate from the holes and then heat oxidated to show an embedded poly-Si 3. Then, a layer left at the contact portion with the gate being masked is removed and the contact holes are made open. Some impurities are added at the holes to complete the dispersion layers 8, 9 as a source, drain region, and then the interconnect structure pattern 11 is placed on them. In this way, the patterns of the gate and contact portions are simultaneously formed and then an alignment margin formed when the contact holes are made may be eliminated. |
