发明名称 CONTROL SYSTEM FOR LINE TRACER
摘要 PURPOSE:To reduce the memory capacity of the line tracer, by measuring the pausing time in the transmission side and also the receiving side and by transmitting paused time or storing correspondence to the received data. CONSTITUTION:When power supply is input to the line tracer, the trace program is loaded from bubble memory BM to buffer RAM of the memory part. At this loading time, if transmission data as well as receiving data are broken, timer TIM provided in panel controller PAC is set, and its time T0 is stored in memory part RAM temporarily. At time T1, when transmission data D1 is input, time T1 is read out from timer TIM, and said time T0 of RAM1 is subtracted from time T1, and resultant time t1 is stored in buffer Buff of memory part RAM. When data D1 terminates, the end time is stored.
申请公布号 JPS56132046(A) 申请公布日期 1981.10.16
申请号 JP19800035070 申请日期 1980.03.19
申请人 FUJITSU LTD 发明人 ISHIBASHI SAKAE
分类号 H04L29/14;G06F13/00;H04L13/00 主分类号 H04L29/14
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