| 摘要 |
PURPOSE:To obtain a level control circuit than can realize a low power consumption and high-speed reading, by forming a voltage dividing circuit having a feedback function with the depression-type MISFET and others and limiting the voltage of a memory matrix input/output line at a certain level. CONSTITUTION:The common input/output line DCOM and anti-DCOM of the static memory cells 1a arranged in a matrix are connected to a voltage dividing circuit consisting of the depression-type MISFETQ17, Q18 and others that receive the voltage of the other end of the serial resistances R1 and R2 with one end connected to the source respectively. A feedback control is given to the conductance of each of the FETQ15 and Q17 which vary their bias diretions due to the variation of the voltage drop of the resistances R1 and R2 in accordance with the levels of the line CDM and anti-CDM corresponding to the storage contents of the selected cells 1a-. Thus the output impedance before the read signal is supplied to the voltage dividing circuit is increased to reduce the power consumption, and at the same time the input voltage is limited at a certain level by a low output impedance to realize a high-speed reading. Such level control circuit can be obtained. |
