| 摘要 |
PURPOSE:To always secure an address stop in a correct timing for an operation controller including an instruction prefetching buffer formed into a chip, by deciding the presence or absence of the address stop in case an instruction is read out of the instruction prefetching buffer. CONSTITUTION:A comparison is given between the memory address to which an application of address stop is desired and the memory address that is used when the 1-chip CPU101 gives an access to the main memory through the address matching mechanism 300 provided outside. When a coincidence is obtained, the AM signal of a bit is delivered to TESTT1. In the normal microprogram leading mode, the external signal group of TESTT1 is taken into the CPU101 along with a microinstruction by the opening of the gate G3. Thus an address stop is always possible in a correct timing by the AM signal. |
