Pulse frequency divider - has variable frequency and ion jitter level achieved using multiplier and flip=flop dividing chain

摘要

The frequency divider has a pulse rate multiplier coupled at the output to a divider comprising a chain of flipflops. Whenever the selected frequency of the output pulse sequence drops below a power of two, a flip flop stage is disconnected from the multiplier (2) and a flip flop stage is connected into the flip flop chain (4). Logic gates are used to switch out stages in the multiplier. Switch-out signals for stages in the multiplier are passed to the gates and simultaneously cause flip flop stages to be switched into the flip flop chain. The circuit reduces jitter at low output frequencies.