发明名称 ADVANCE CONTROL TYPE INFORMATION PROCESSING EQUIPMENT
摘要 PURPOSE:To raise the probability of address coincidence of each address and store address of the instruction which has been taken in advance by a small quantity of hardware, and rewrite and detect the advance instruction, by comparing the final address of continuous instruction word with the advance instruction address. CONSTITUTION:An instruction which has been fetched in advance from the memory device 1 is stored in the instruction buffer register 2 having plural registers, the instruction from the register 2 is stored in order to the instruction source register 3, and in response to the instruction from this register 3, a store address is generated from the address generating circuit 4. Also, the instruction from the register 3 is executed by the arithmetic circuit 7, the address which is in the course of execution of this operation is stored in the execution instruction address register 5, and the address of the final instruction among the continuous advance instructions which have been stored in the advance instruction address register 6. And, the coincidence of each address of the registers 5, 6 and the store address which has been generated by the circuit 4 is compared by the coincidence circuits 8, 9, by which the probability of address coincidence is raised.
申请公布号 JPS56124954(A) 申请公布日期 1981.09.30
申请号 JP19800027531 申请日期 1980.03.05
申请人 NIPPON ELECTRIC CO 发明人 HANATANI SHIYUUICHI
分类号 G06F9/38;(IPC1-7):06F9/38 主分类号 G06F9/38
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