发明名称 ADDRESS CIRCUIT FOR IMAGE MEMORY
摘要 <p>PURPOSE:To confirm the operation of a logical circuit without increasing the number of IC output terminals by using an external IC terminal to be a data output in normal memory operation as an address confirming terminal in the case of including the logical circuit in a memory. CONSTITUTION:In normal memory operation, an address selecting circuit 7 selects an address input terminal 6 and an inputted signal is entered into an address register 8 and led into an address decoder 13. A data selecting circuit 10 selects a reading means 5 and data read out from a memory cell 4 is led into an output terminal 2. When a test signal is turned to a low level, an address shifted by an address shifting circuit 9 is selected by the circuit 7 and inputted to the register 8. Thereby, one bit of the address is successively shifted and outputted from the terminal 2. Since the address stored in the same IC as the memory can be outputted from the terminal in the test mode, the operation of an address generating circuit can be easily confirmed.</p>
申请公布号 JPS63316595(A) 申请公布日期 1988.12.23
申请号 JP19870151129 申请日期 1987.06.19
申请人 HITACHI LTD 发明人 NAKAJIMA MITSUO;MATSUMOTO SHUZO;KOJIMA NOBORU;OKAMURA TAKUMI;NAKAGAWA HIMIO
分类号 G09G5/39;G06F12/00;G06T1/60;G09G1/02;G09G5/00;G11C11/401;G11C29/00;G11C29/12;H04N9/16;H04N11/04;H04N17/06 主分类号 G09G5/39
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