| 摘要 |
PURPOSE:To make it possible to turn off a thyristor inverter and prevent such an inconvenience as a drop in gate current source of a valve, by locking for a single time or plural times or for a set duration of time gate pulses to be output after a set interval after a by-passed switch-on signal is generated. CONSTITUTION:When a by-pass switch-on signal (C), a turn-off signal (g) for a U-phase valve 12 and a forward voltage signal FV are input to an AND gate 19, an output signal (h) is inputted to a timer circuit 20 and a signal (i) of an ''on'' period is outputted. The signal (i) is inputted to a pulse circuit 21 and a signal (j) with a set pulse width is generated in a rise time of the first shot of the signal (h). The AND gate 22, with both a gate pulse (f) output from a pulse circuit 18 and the signal (j) as the input signals, locks the gate pulse (f) while the signal (j) is outputted and prevent the gate pulse from being output to a valve 12. |
