| 摘要 |
<p>PURPOSE:To obtain the value of greater delay without increasing occupied area, by connecting depletion type MISFET grounded for the gate, between one input terminal and another output terminal of two stages of inverters. CONSTITUTION:Between the output terminal A of the 1st stage inverter consisting of a depletion type load MISFETTR1 and enhancement type driving MISFETTER2 and the input terminal B of the 2nd stage inverter consisting similar two MISFETs TR3, TR4, a depletion type MISFETTR5 in which one of the source or drain is connected to the terminal A and another is connected to the terminal B and the gate is grounded, is connected. Further, when the potential level of the input terminal In changes from high to low level, the level at the output terminal Out is at a low level with a delay, but when changes to high level, no delay is given.</p> |
