| 摘要 |
PURPOSE:To reduce ON resistance of insulation gate FET of high pressure-resistance by providing an offset region between a channel and a drain in and on a substrate semiconductor and by laminating three or more layers of semiconductor having different conductive types between adjacent layers. CONSTITUTION:There are N<+> type source and drain 2, 3 in a P type Si substrate 1. An N<-> layer 9 and a P <-> layer 10 are piled, an N type intermediate layer 11 is provided, and thereby a gate region and an offset gate region of multilayer structure are connected, through which current is made to flow. By flowing high-resistance layers of P<-> and N<-> into offset gate regions alternately in this way, the N<-> layer is depleted between the parts of the P type Si substrate of the P layers, absorbing the rise of voltage. When the density of impurity of the P<-> layer is selected properly and the layer is depleted completely between the same and the adjacent N<-> layer at the time of rise of the drain voltage, the fall of pressure resistance of the drain due to the multilayer structure can be prevented. By this constitution, it becomes possible to increase the N<-> high-resistance layers through which current flows, to lessen the resistance of the offset gate regions and to reduce the ON resistance of the element. |
